1. Field of the Invention
The present invention relates to an integrated arithmetic unit for use in the field of computation and more particularly to computation in which precision multiplication is required. The arithmetic unit is for use in digital filters, correlation, convolution, polynomial evaluation or squaring. The design is optimized for integration and for flexible interconnection with other like units, or delay units, and for assembly into more complex computing systems.
2. Description of the Prior Art
The invention is applicable to a wide variety of digital computations. In digital filters, for instance, wherein recursive or integrative feedback loops occur, prior art filters frequently employ arithmetic means which introduce an appreciable error into the computation. The error occurs in the use of less than double precision multiplication, or in the use of truncation in the operands. If double precision is retained, there is great difficulty in contending with word growth, particularly when many functions are combined in a single integrated circuit.
The present invention represents an outgrowth of earlier work described in U.S. Pat. No. 4,020,334 of Noble R. Powell and John M. Irwin, entitled "Integrated Arithmetic Unit for Computing Summed Indexed Products." In that patent, a series of functions involving summation, single precision multiplication means and summation are combined in a single integrated circuit unit. The unit also contains a second single precision multiplication means which, together with the first multiplication, performs vector matrix multiplication. A primary application of that unit is in computation of the fast fourier transform. Also relevant to the present invention is U.S. Pat. No. 3,947,670 entitled "Signed Multiplication Logic" of John M. Irwin et al, which discloses the multiplication logic for obtaining a single precision product. The partial product stages described therein form truncated partial products suitable for formation of a single precision product. Filed concurrently herewith is an application Ser. No. 811,193 of John M. Irwin entitled "Signed Double Precision Multiplication Logic." This application treats the multiplication logic, which is used in the arithmetic unit and digital networks treated herein.